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INT5130CS

Integrated Powerline MAC/PHY Transceiver

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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

accessed from the SPI Slave port when the MDI_SPIS_N select line has been tied low to select the SPI

Slave port.

PLCSR

Register Name

MII Mandated

0

Control Register

X

1

Status Register

X

Table 5: Powerline Control and Status Register (PLCSR) Summary

PRE ST OP PHYAD REGAD TA

Data

Idle

READ 1...1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD Z

WRITE 1...1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Z

Figure 13: MDI Frame Structure

PRE (Preamble)

At the beginning of each MDI transaction, the external host shall send a sequence of 32 contiguous

logic “1” bits on the MDIO signal so the INT5130 can establish synchronization. The INT5130

needs to observe this 32 bit sequence on the MII_MDIO signal before it responds to any

transaction.

ST (Start of Frame)

Indicated by a “01” pattern.

OP (Operation Code)

“10” indicates a READ. “01” indicates a WRITE.

PHYAD (PHY Address)

The PHY Address is 5 bits, allowing up the 32 unique PHY addresses. The INT5130 will respond to

PHY addresses indicated by 0bXX000. The “XX” bits of the PHY address are controlled by the

INT5130 interface pins MDI_ADRSEL(0:1). This allows the designer to assign the INT5130 to one

of 4 unique PHY addresses.

REGAD (Register Address)

The Register Address is 5 bits and is used to index the maximum of 32 individual registers in the

MDI address space. The INT5130 only implements the two mandated MII registers. 0b00000 will

index the MII Control Register and 0b00001 will index the MII Status Register.

TA (Turnaround)

The turnaround time is a 2 bit time spacing between the Register Address field and the Data field to

avoid contention during a read transaction.

For reads, both the external host and the INT5130 will remain in tri-state for the first bit time. The

INT5130 will drive a “0” during the second bit time.

INTELLON CONFIDENTIAL

19

Rev 8.1

ADVANCE INFORMATION

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