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INT5130CS

Integrated Powerline MAC/PHY Transceiver

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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

Data

Data sent over the MII interface consists of N bytes of data transmitted as 2N nibbles.

The de-assertion of the MII_TXEN signals the End Of Frame (EOF) for data transmitted on the

MII_TX[3:0] pins. Likewise, the de-assertion of the MII_RXDV signals the EOF for data transmitted on

MII_RX[3:0].

MACs Serial Bit Stream

LSB D0 D1 D2 D3 D4 D5 D6 D7 MSB

LSB D0

First nibble

Second nibble

MII

D1

Nibble

Stream D2

MSB D3

Figure 10: Partition of Serial Bit Stream to Nibble Stream

MDI Control Interface

The Management Data Interface connects the external host to the INT5130 for purposes of controlling the

INT5130 and gathering status. A specific frame format and protocol definition exists for exchanging

management frames over this interface. A register definition exists as well that specifies a basic register

set with an extension mechanism. The INT5130 implements the basic register set only.

MDI Timing Diagrams

MII_MDCLK

tMDI_RVAL

MII_MDIO

DATA

Figure 11: MDI Receive Timing Diagram

INTELLON CONFIDENTIAL

17

Rev 8.1

ADVANCE INFORMATION

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