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INT5130CS

Integrated Powerline MAC/PHY Transceiver

Unspecified 

INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

MII Signal Descriptions

The following description references Clause 22, Media Independent Interface specification, used in the

100 Mbps half-duplex mode. The MII is used as a data channel that transfers data back and forth with

flow controlled by the carrier sense signal (MII_CRS).

MII_TXCLK and MII_RXCLK

The INT5130 generates a stable, continuous 25 MHz square wave that is supplied on MII_TXCLK

and MII_RXCLK. These clocks provide the timing reference for the transfer of the MII_TXEN and

MII_TX signals, as well as MII_RX, MII_RX_ER, and MII_RXDV.

MII_RX_ER

MII_RX_ER is activated when the INT5130 detects an error in the receive stream as a result of

decoding.

MII_TX_ER

MII_TX_ER is activated by the external host controller when an error condition is detected during

packet transmission. The INT5130 will ignore any MII transmission within which MII_TX_ER is

asserted. MII_TX_ER is ignored if MII_TXEN is not asserted.

MII_TXEN

MII_TXEN from the external host provides the framing for the Ethernet packet. An active

MII_TXEN indicates to the INT5130 that data on MII_TX[3:0] should be sampled using MII_TXCLK.

MII_TX[3:0]

MII_TX[3:0] contains the data to be transmitted and transitions synchronously with respect to

MII_TXCLK. MII_TX[0] is the least significant bit. It is generally assumed that the data will contain

a properly formatted Ethernet frame. That is, the first bits on MII_TX[3:0] correspond to the

preamble, followed by SFD and the rest of the Ethernet frame (DA, SA, length/type, data, CRC).

MII_RXDV

MII_RXDV is asserted by the INT5130 to indicate that the INT5130 has decoded receive data to

present to the external host.

MII_RX[3:0]

MII_RX[3:0] contains the data recovered from the medium by the INT5130 and transitions

synchronously with respect to MII_RXCLK. MII_RX[0] is the least-significant bit. The INT5130

formats the frame such that the external MAC will be presented with expected preamble plus SFD.

MII_CRS

MII_CRS is used to tell the external host when the INT5130 is available for sending a packet.

MII_CRS is asynchronous to MII_TXCLK. When a packet is being transmitted, CRS is held high.

CRS will go low whenever the INT5130 is ready to accept another packet.

On transmit, the INT5130 asserts MII_CRS some time after MII_TXEN becomes active, and drops

MII_CRS after MII_TXEN goes inactive AND when the INT5130 is ready to receive another packet

from the external host for transmission. When MII_CRS has been negated for at least 900ns, the

external MAC may assert MII_TXEN again if there is another packet to send. This differs from

nominal behavior of MII_CRS in that MII_CRS can extend past the end of the packet by an

INTELLON CONFIDENTIAL

14

Rev 8.1

ADVANCE INFORMATION

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