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INT5130CS

Integrated Powerline MAC/PHY Transceiver

Unspecified 

INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

MII_CRS

MII_TXEN

MII_TX[3:1], MII_TX0

P

P

P

MII_RX[3:0]

P

MII_RXDV

MII_COL

Case 6

TX only

Case 7

TX overrun

Frame

dropped

Figure 9: MII Flow Control Overview Part 2

Case 8

Collision

MII Frame Structure

The frame structure transmitted on the MII or GPSI interface is the following sequence of fields:

Interframe Gap

Preamble

Start Frame Delimiter

Data

Interframe Gap

A period on the MII interface during which no data activity occurs on the MII.

Preamble

Begins a frame transmission that consists of 7 octets with the following bit values…

10101010 10101010 10101010 10101010 10101010 10101010 10101010

The preamble is stripped by the INT5130 when transmitting (the preamble is not transmitted on the

PLC medium) and pre-pended by the INT5130 when receiving.

Start Frame Delimiter

Indicates the start of a frame and follows the preamble. The SFD bit sequence is 10101011.

The start frame delimiter is stripped by the INT5130 when transmitting (the SFD is not transmitted

on the PLC medium) and pre-pended by the INT5130 when receiving.

INTELLON CONFIDENTIAL

16

Rev 8.1

ADVANCE INFORMATION

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