IDT72V36103 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72V36103

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36

Integrated Device Technology 

IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36

CLKA

4

1

2

COMMERCIAL TEMPERATURE RANGE

RS1

tFSS

FS2

tFSS

FS1,FS0

0,0

tFSH

tFSH

FF/IR

ENA

A0-A35

NOTE:

1. CSA = LOW, W/RA = HIGH, MBA = LOW.

tWFF

tENS2

tENH

tDS

tDH

AF Offset

(Y)

AE Offset

(X)

First Word to FIFO1

4678 drw 07

Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(IDT Standard and FWFT Modes)

CLKA

4

RS1

tFSS

tFSH

FS2

FF/IR

tFSS

FS1/SEN

tSPH

tSENS

tSENH

tSENS

tSENH

tSDS

tSDH

tSDS

tSDH

FS0/SD(2)

AF Offset

(Y) MSB

AE Offset

(X) LSB

NOTES:

1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FF/IR is set HIGH.

2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).

tWFF

Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(IDT Standard and FWFT Modes)

17

4678 drw 08

Share Link: