IDT72V36103 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72V36103

3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36

Integrated Device Technology 

IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36

CLKA

COMMERCIAL TEMPERATURE RANGE

1

2

CLKB

RS1, RS2

BE/FWFT

tRSTS

FS2,

FS1,FS0

FF/IR

EF/OR

tRSF

AE

tRSF

AF

MBF1,

tRSF

MBF2

RTM LOW

tWFF

tBES

tFSS

tRSTH

tBEH

BE

tFWS

tFSH

0,1

tREF(2)

FWFT

tWFF

NOTES:

1. PRS must be HIGH during Reset.

2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 3. Reset and Loading X and Y with a Preset Value of Eight (IDT Standard and FWFT Modes)

4678 drw 05

CLKA

CLKB

PRS

FF/IR

tRSTS

EF/OR

AE

AF

MBF1,

MBF2

RTM LOW

tRSF

tRSF

tRSF

tWFF

tRSTH

tREF (2)

NOTES:

1. RS1 must be HIGH during Partial Reset.

2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 4. Partial Reset (IDT Standard and FWFT Modes)

16

tWFF

4678 drw 06

Share Link: