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IDT71342SA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

Integrated Device Technology 

IDT71342SA/LA

High-Speed 4K x 8 Dual-Port Static RAM with Semaphore

Industrial and Commercial Temperature Ranges

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)

tWC

ADDRESS

OE

CE or SEM(9)

R/W

DATAOUT

DATAIN

tAS (6)

tAW

tWP (2)

tLZ

tWZ (7)

(4)

tWR(3)

tHZ (7)

tOW

tDW

tHZ (7)

(4)

tDH

2721 drw 10

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)

tWC

ADDRESS

CE or SEM(9)

R/W

DATAIN

tAS(6)

tAW

tEW (2)

tDW

tWR(3)

tDH

2721 drw 11

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus

for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access SRAM, CE =VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

6.942

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