IDT71342SA Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71342SA Datasheet PDF : 14 Pages
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IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage(5)
71342X20
Com'l Only
71342X25
Com'l & Ind
71342X35
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
20
____
25
____
35
____
ns
tEW
Chip Enable to End-of-Write(3)
15
____
20
____
30
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
15
____
20
____
25
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
15
____
20
____
ns
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(4)
tWZ
Write Enable to Output in High-Z(1,2)
____
15
____
15
____
20
ns
0
____
0
____
3
____
ns
____
15
____
15
____
20
ns
tOW
Output Active from End-of-Write(1,2,4)
3
____
3
____
3
____
ns
tSWR
SEM Flag Write to Read Time
10
____
10
____
10
____
ns
tSPS
SEM Flag Contention Window
10
____
10
____
10
____
ns
71342X45
Com'l Only
71342X55
Com'l & Ind
71342X70
Com'l Only
2721 tbl 10a
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
45
____
55
____
70
____
ns
40
____
50
____
60
____
ns
tAW
Address Valid to End-of-Write
40
____
50
____
60
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
40
____
50
____
60
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
25
____
30
____
ns
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(4)
____
20
____
25
____
30
ns
3
____
3
____
3
____
ns
tWZ
Write Enable to Output in High-Z(1,2)
____
20
____
25
____
30
ns
tOW
Output Active from End-of-Write(1,2,4)
3
____
3
____
3
____
ns
tSWR
SEM Flag Write to Read Time
10
____
10
____
10
____
ns
tSPS
SEM Flag Contention Window
10
____
10
____
10
____
ns
NOTES:
2721 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
6.842
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