IDT71342SA Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71342SA Datasheet PDF : 14 Pages
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IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
tRC
ADDRESS
tAA or tSAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2721 drw 07
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
CE or SEM (5)
tSOP
tSOP
tACE
tAOE(4)
tHZ(2)
OE
DATAOUT
ICC
CURRENT
ISB
tLZ (1)
tLZ (1)
tPU
50%
VALID DATA(4)
tHZ (2)
tPD
50%
2721 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA
5. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and tSAA is for Semaphore Address Access.
Timing Waveform of Write with Port-to-Port Read(2,3)
tWC
ADDR "A"
MATCH
R/W
(1)
"A"
tWP
tDH
tDW
DATAIN "A"
VALID
ADDR "B"
DATAOUT "B"
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. CE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
MATCH
tWDD
tDDD
VALID
2721 drw 09
6.742
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