IDT70P3517 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT70P3517

512K/256K x36 SYNCHRONOUS DUAL QDR-II™

Integrated Device Technology 

18/9Mb x36 IDT70P3537/70P3517

SYNCHRONOUS Dual QDR-IITM

Truth Table III - Port Enable Pins(1)

Normal Read and Writes

Device Selected

EP[0]

EP[1]

E[0]

E[1]

Bank 0

VSS

VSS

L

L

Bank 1

VDD

VSS

H

L

Bank 2

VSS

VDD

L

H

Bank 3

VDD

VDD

H

H

NOTES:

5677 tbl05

1. EP [1:0] - Port Enable Programming Polarity (see pin description for the entire device).

2. Ex[1:0] - Port Enable (see pin description assigned for each port).

Preliminary Datasheet

Commercial Temperatue Range

Cascade/Multi-Drop using Port Enable (E0 & E1) Pins

As shown below in Figure 1 upto four devices can be cascaded using the Port Enable (E0,E1) pins scheme. The port enable pins

are subject to the same DC characteristics as the QDR interface. Refer to Pin Definitions table for pin descriptions. This diagram illustrates

one port of a QDR-II dual port

Figure 1. Multi-drop Cascading using the Chip Enable E[1:0] Pins

7

July 16, 2007

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