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IDT70P3517

512K/256K x36 SYNCHRONOUS DUAL QDR-II™

Integrated Device Technology 

18/9Mb x36 IDT70P3537/70P3517

SYNCHRONOUS Dual QDR-IITM

Preliminary Datasheet

Commercial Temperatue Range

two. The user may disable the DLL by holding DOFF low. With the DLL

off, the C and C (or K and K, if C and C are not used) will directly clock

the output register of the IDT70P3537/70P3517. With the DLL off,

there will be a propagation delay from the time the clock enters the

device until the data appears at the output. QDR-II becomes QDRITM

with DLL off. First data out is referenced to C instead of C.

Echo Clock

The echo clocks, CQ and CQ, are generated by the C and C

clocks (or K, K if C, C are disabled). The rising edge of C generates

the rising edge of CQ, and the falling edge of CQ. The rising edge of

C generates the rising edge of CQ and the falling edge of CQ. This

scheme improves the correlation of the rising and falling edges of the

echo clock and will improve the duty cycle of the individual signals.

The echo clock is very closely aligned with the data, guaranteeing

that the echo clock will remain closely correlated with the data, within

the tolerances designated.

Normal QDR write cycles are initiated by holding the write port select

(W) low at K rising edge. Also, the Byte Write inputs (BW0-3), desig-

nating which bytes are to be written, need to be held low for both the

K and K clocks. On the rising edge of K the first word of the data must

also be present on the data input bus D[35:0] observing the designated

set up times. Upon the rising edge of K the first word of the burst will

be latched into the input register. After K has risen, and the designated

hold times observed, the second half of the clock cycle is initiated by

presenting the write address to the address bus A[X:0], the BW0-3

inputs for the second data word of the burst, and the second data item

of the burst to the data bus D[35:0]. Upon the rising edge of K, the

second word of the burst will be latched, along with the designated

address. Both the first and second words of the burst will be written

into memory as designated by the address and byte write enables.

The addresses for the write cycles is provided at the K rising edge,

and data is expected at the rising edge of K and K, beginning at the

same K that initiated the cycle.

Normal QDR-II Read and Write Operations

The IDT70P3537/70P3517 Dual QDR-II Static RAM supports

QDR-II burst-of-two read/write operations. Read operations are initi-

ated by holding the read port select (R) low, and presenting the read

address to the address port during the rising edge of K which will latch

the address. Data is delivered after the next rising edge of the next K

(t + 1), using C and C as the output timing references; or K and K, if

C and C are tied high.

The write operation is a standard QDR-II burst-of-two write

operation, except the data is not available to be read until the next

clock cycle (this is one cycle later than standard QDR-II SRAM).

Programmable Impedance

An external resistor, RQ, must be connected between the

ZQ pin on the IDT70P3537/70P3517 and tied to VSS to allow the

IDT70P3537/70P3517 to adjust its output drive impedance. The value

of RQ must be 5X the value of the intended drive impedance of the

IDT70P3537/70P3517. The allowable range of RQ to guarantee

impedance matching with a tolerance of +/- 15% is 175 ohms to 350

ohms. The output impedance is adjusted every 1024 clock cycles to

correct for drifts in supply voltage and temperature. If the user wishes

to drive the output impedance of the IDT70P3537/70P3517 to its

lowest value, the ZQ pin may be tied to VDDQ.

4

July 16, 2007

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