IDT70P3517 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT70P3517 Datasheet PDF : 20 Pages
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18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet
Commercial Temperatue Range
Pin Definitions
Symbol(1) Pin Function
Description
D[35:0]X
BW0X, BW1X,
BW2X, BW3X
A[17:0]X(2)
Q[35:0]X
Input
Synchronous
Input
Synchronous
Input
Synchronous
Output
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is
written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the
data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18], and BW3 controls D[35:27].
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K
clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs
are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[35:0] are automatically tri-stated.
WX
Input
Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will
Synchronous deselect the Write port. Deselecting the Write port will cause D[35:0] to be ignored.
RX
Input
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the
Synchronous Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next
rising edge of the C clock. (DOFFX = 1). Each read access consists of a burst of two sequential transfers.
CX
Input Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further details.
CX
Input Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times
of various devices on the board back to the controller. See application example for further details.
KX
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[35:0] when in single clock mode.
All accesses are initiated on the rising edge of K.
KX
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device. Drives out data through Q[35:0] when in single clock mode.
CQX
CQX
ZQX
EP[1:0]
EX[1:0]
DOFFX
MRST
DEPTH
TDO
TCK
TDI
TMS
TRST
INC
VREFX
VDD
VSS
VDDQX
Output Clock Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop when the output data is tri-stated.
Output Clock
Synchronous Echo Clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop wehen the output data is tri-stated.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[35:0] output impedance is set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode.
This pin cannot be connected directly to GND or left unconnected.
Input
EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use
Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins.
Input
Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3537 devices. If a customer
Syncronous does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop
using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of K for write operations.
Input
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet.
There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured.
Input
Master Reset pin. When held low will reset the device.
Asynchronous
Input
Connect to VDDQ for 9Mb. Connect to VSS for 18Mb.
Output TDO pin for JTAG.
Input
TCK pin for JTAG.
Input
TDI pin for JTAG.
Input
TMS pin for JTAG.
Input
Reset pin for JTAG.
Asynchronous
Should be tied to VCC or VSS only, or can be left as a floating pin.
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground Ground for the device. Should be connected to ground of the system.
Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
5677 tbl 01
NOTE:
1. "X" = "L" for the Left Port pins and "X" = "R" for the Right Port pins.
2. A[16:0]x for IDT70P3517.
5
July 16, 2007
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