IDT7006S(2018) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT7006S Datasheet PDF : 21 Pages
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IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2739 tbl 12
DATAOUT
BUSY
INT
775Ω
5V
1250Ω
30pF
Figure 1. AC Output Test Load
AC Electrical Oharacteristics Over the
Operating temperature and Supply Voltage Range(4)
DATAOUT
775Ω
5V
1250Ω
5pF*
,
2739 drw 06
Figure 2. Output Test Load
(5pF for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
7006X15
Com'l Only
7006X17
Com'l Only
7006X20
Com'l,Ind
& Military
7006X25
Com'l & Military
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
____
17
____
20
____
25
____
ns
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
____
15
____
17
____
20
____
25
ns
____
15
____
17
____
20
____
25
ns
tAOE
Output Enable Access Time
____
10
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1,2)
tHZ
Output High-Z Time(1,2)
tPU
Chip Enable to Power Up Time (2,5)
tPD
Chip Disab le to Power Down Time (2,5)
3
____
3
____
3
____
3
____
ns
3
____
3
____
3
____
3
____
ns
____
10
____
10
____
12
____
15
ns
0
____
0
____
0
____
0
____
ns
____
15
____
17
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
10
____
10
____
ns
tSAA
Semaphore Address Access Time
____
15
____
17
____
20
____
25
ns
7006X35
Com'l &
Military
7006X55
Com'l, Ind
& Military
2739 tbl 13a
7006X70
Military
Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
70
____
ns
tAA
Address Access Time
tACE
Chip Enable Access Time(3)
____
35
____
55
____
70
ns
____
35
____
55
____
70
ns
tAOE
Output Enable Access Time
____
20
____
30
____
35
ns
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time(1,2)
tHZ
Output High-Z Time(1,2)
tPU
Chip Enab le to Power Up Time (2,5)
tPD
Chip Disable to Power Down Time (2,5)
3
____
3
____
3
____
ns
3
____
3
____
3
____
ns
____
15
____
25
____
30
ns
0
____
0
____
0
____
ns
____
35
____
50
____
50
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
____
15
____
15
____
ns
tSAA
Semaphore Address Access Time
____
35
____
55
____
70
ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
2739 tbl 13b
6.742
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