IDT7006S(2018) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT7006S Datasheet PDF : 21 Pages
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HIGH-SPEED
IDT7006S/L
16K x 8 DUAL-PORT
STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
◆ Low-power operation
– IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7006L
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆ IDT7006 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
◆ M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆ Busy and Interrupt Flags
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Devices are capable of withstanding greater than 2001V
electrostatic discharge
◆ Battery backup operation—2V data retention
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
TQFP
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A13L
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
14
CER
OER
R/WR
SEML
INTL(2)
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2018 Integrated Device Technology, Inc.
M/S
1
I/O0R-I/O7R
BUSYR(1,2)
A13R
A0R
SEMR
INTR(2)
2739 drw 01
JULY 2018
DSC- 2739/18
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