8405202QA Просмотр технического описания (PDF) - Intersil
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8405202QA Datasheet PDF : 37 Pages
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80C86
VCC
GND
VCC
82C8A/85
CLOCK
GENERATOR
RES
RDY
MN/MX
M/IO
CLK INTA
READY RD
WR
RESET
DT/R
DEN
WAIT
STATE
GENERATOR
ALE
80C86
CPU
GND
1
C1
AD0-AD15
A16-A19
GND
20
BHE
C2
40 VCC
C1 = C2 = 0.1µF
VCC
GND
ADDR/DATA
STB
OE
82C82
LATCH
2 OR 3
T
OE
82C86
TRANSCEIVER
(2)
DATA
A0
BHE
ADDR
OPTIONAL
FOR INCREASED
DATA BUS DRIVE
EH
EL
WG
HM-6516
CMOS RAM
2k x 8
2k x 8
E
G
HM-6616
CMOS PROM (2)
2k x 8 2k x 8
CS RD WR
CMOS
82CXX
PERIPHERALS
FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION
VCC
GND
VCC
82C84A/85
CLOCK
GENERATOR/
RES
RDY
MN/MX
CLK
S0
READY S1
RESET S2
80C86
CPU
WAIT
STATE
GENERATOR
LOCK
GND AD0-AD15
1
A16-A19
C1
BHE
GND
20
C2
40 VCC
C1 = C2 = 0.1µF
GND
NC
GND
ADDR/DATA
CLK MRDC
S0
MWTC
S1
82C88
BUS
AMWC
NC
S2 CTRLR IORC
DEN
IOWC
DT/R
AIOWC NC
ALE
INTA
STB
OE
82C82
(2 OR 3)
ADDR
T
OE
82C86
TRANSCEIVER
(2)
DATA
A0
BHE
EH
EL
WG
HM-65162
CMOS RAM
2k x 8
2k x 8
E
G
HM-6616
CMOS PROM (2)
2k x 8 2k x 8
CS RDWR
CMOS
82CXX
PERIPHERALS
FIGURE 6B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION
16
FN2957.3
January 9, 2009
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