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ICS663

PLL BUILDING BLOCK

Integrated Device Technology 

ICS663

PLL BUILDING BLOCK

PLL BUILDING BLOCK

Determining the Loop Filter Values

The loop filter components consist of C1, C2, and RZ.

Calculating these values is best illustrated by an example.

Using the example in Figure 1, we can synthesize 20 MHz

from a 200 kHz input.

The phase locked loop may be approximately described by

the following equations:

Bandwidth= (---R----Z----⋅--2---π-K----⋅-O----N-⋅-----I---C---P---)

Damping factor,ζ= -R--2--Z- K-----O-----⋅------I-N-C---P----⋅------C----1-

where:

KO = VCO gain (MHz/Volt)

Icp = Charge pump current (µA)

N = Total feedback divide from VCO,

including the internal VCO post divider

C1 = Loop filter capacitor (Farads)

RZ = Loop filter resistor (Ohms)

As a general rule, the bandwidth should be at least 20 times

less than the reference frequency, i.e.,

BW ≤(REFIN) ⁄ 20

In this example, using the above equation, bandwidth

should be less than or equal to 10 kHz. By setting the

bandwith to 10kHz and using the first equation, RZ can be

determined since all other variables are known. In the

example of Figure 1, N = 200, comprising the divide by 2 on

the chip (VCO post divider) and the external divide by 100.

Therefore, the bandwidth equation becomes:

0,000 = -R----Z---2-⋅---π---2-⋅--0---0-2---0⋅---0---2---.--5-

Choosing a damping factor of 0.7 (a minimal damping factor

than can be used to ensure fast lock time), damping factor

equation becomes:

.7 = 2---5----,--2--0---0---0-- --2---0---0-----⋅---2--2-0--.-0-5----⋅------C---

and C1 = 1.25 nF (1.2 nF is the nearest standard value).

The capacitor C2 is used to damp transients from the

charge pump and should be approximately 1/20th the size

of C1, i.e.,

C2 ≅ C1 ⁄ 20

Therefore, C2 = 60 pF (56 pF nearest standard value).

To summarize, the loop filter components are:

C1 = 1.2 nf

C2 = 56 pf

Rz = 25 kΩ

and RZ = 25 kΩ

IDT™ / ICS™ PLL BUILDING BLOCK

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ICS663

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