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ICS663

PLL BUILDING BLOCK

Integrated Device Technology 

ICS663

PLL BUILDING BLOCK

PLL BUILDING BLOCK

External Components

Avoiding PLL Lockup

The ICS663 requires a minimum number of external

components for proper operation. A decoupling capacitor of

0.01µF should be connected between VDD and GND as

close to the ICS663 as possible. A series termination

resistor of 33Ω may be used at the clock output.

Special considerations must be made in choosing loop

components C1 and C2:

1) The loop capacitors should be a low-leakage type to

avoid leakage-induced phase noise. For this reason, DO

NOT use any type of polarized or electrolytic capacitors.

2) Microphonics (mechanical board vibration) can also

induce output phase noise when the loop bandwidth is less

than 1 kHz. For this reason, ceramic capacitors should have

C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and

X7R. These and some other ceramics have piezoelectric

properties that convert mechanical vibration into voltage

noise that interferes with VCXO operation.

For larger loop capacitor values such as 0.1µF or 1µF, PPS

film types made by Panasonic, or metal poly types made by

Murata or Cornell Dubilier are recommended.

For questions or changes regarding loop filter

characteristics, please contact your sales area FAE, or IDT

Applications.

In some applications, the ICS663 can “lock up” at the

maximum VCO frequency. The way to avoid this problem is

to use an external divider that always operates correctly

regardless of the CLK output frequency. The CLK output

frequency may be up to 2x the maximum Output Clock

Frequency listed in the AC Electrical Characteristics above

when the device is in an unlocked condition. Make sure that

the external divider can operate up to this frequency.

Explanation of Operation

The ICS663 is a PLL building block circuit that includes an

integrated VCO with a wide operating range. The device

uses external PLL loop filter components which through

proper configuration allow for low input clock reference

frequencies, such as a 15.7 kHz Hsync input.

The phase/frequency detector compares the falling edges of

the clocks inputted to FBIN and REFIN. It then generates an

error signal to the charge pump, which produces a charge

proportional to this error. The external loop filter integrates

this charge, producing a voltage that then controls the

frequency of the VCO. This process continues until the

edges of FBIN are aligned with the edges of the REFIN

clock, at which point the output frequency will be locked to

the input frequency.

Figure 1. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference

0.01µ F

200 kHz

+3.3 or 5 V

C2

VDD SEL

RZ C1

LF

LFR

REFIN

FBIN

IC S 6 6 3

CLK

GND

20 MHz

200 kHz

100

Digital Divider such as

ICS674-01

IDT™ / ICS™ PLL BUILDING BLOCK

5

ICS663

REV E 012006

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