P4C163-25CM Просмотр технического описания (PDF) - Performance Semiconductor

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P4C163-25CM

ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS

Performance Semiconductor 

READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

(9)

t RC

ADDRESS

DATA OUT

t AA

t OH

PREVIOUS DATA VALID

P4C163/163L

DATA VALID

READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)

tRC

CE 1

CE 2

DATA OUT

I CC

VCC SUPPLY

CURRENT I SB

tAC (10)

(8,10)

t LZ

(10)

t PU

t HZ(8,10)

DATA VALID

t

(10)

PD

HIGH IMPEDANCE

Notes:

9. READ Cycle Time is measured from the last valid address to the first

transitioning address.

10. Transitions caused by a chip enable control have similar delays

irrespective

of

whether

CE

1

or

CE2

causes

them.

113

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