CY7C1484V33-167 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1484V33-167 Datasheet PDF : 29 Pages
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PRELIMINARY
CY7C1484V33
CY7C1485V33
Interleaved Burst Sequence
First
Address
A[1:0]]
00
01
10
11
Second
Address
A[1:0]
01
00
11
10
Third
Address
A[1:0]
10
11
00
01
Linear Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
10
11
00
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
Fourth
Address
A[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Parameter
IDDZZ
tZZS
tZZREC
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Cycle Descriptions [1, 2, 3, 4]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
Min.
2tCYC
Max.
TBD
2tCYC
Unit
mA
ns
ns
Next Cycle Add. Used ZZ
Unselected
None
0
CE3 CE2 CE1 ADSP ADSC ADV OE
X
X
1
X
0
X
X
Unselected
None
0
1
X
0
0
X
X
X
Unselected
None
0
X
0
0
0
X
X
X
Unselected
None
0
1
X
0
1
0
X
X
Unselected
None
0
X
0
0
1
0
X
X
Begin Read
External
0
0
1
0
0
X
X
X
Begin Read
External
0
0
1
0
1
0
X
X
Continue Read Next
0
X
X
X
1
1
0
1
Continue Read Next
0
X
X
X
1
1
0
0
Continue Read Next
0
X
X
1
X
1
0
1
Continue Read Next
0
X
X
1
X
1
0
0
Suspend Read Current
0
X
X
X
1
1
1
1
Suspend Read Current
0
X
X
X
1
1
1
0
Suspend Read Current
0
X
X
1
X
1
1
1
Suspend Read Current
0
X
X
1
X
1
1
0
Begin Write
Current
0
X
X
X
1
1
1
X
Begin Write
Current
0
X
X
1
X
1
1
X
Begin Write
External
0
0
1
0
1
0
X
X
Notes:
1. X = “Don’t Care.” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
DQ Write
Hi-Z
X
Hi-Z
X
Hi-Z
X
Hi-Z
X
Hi-Z
X
Hi-Z
X
Hi-Z Read
Hi-Z Read
DQ Read
Hi-Z Read
DQ Read
Hi-Z Read
DQ Read
Hi-Z Read
DQ Read
Hi-Z Write
Hi-Z Write
Hi-Z Write
Document #: 38-05285 Rev. *A
Page 8 of 29
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