CY7C1484V33-167 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1484V33-167

2M x 36/4M x 18 Pipelined DCD SRAM

Cypress Semiconductor 

Logic Block Diagram

CY7C1484V33–2M × 36

CLK

ADV

ADSC

ADSP

A[20:0]

21

GW

BWE

BW d

BWc

BWb

BWa

CE1

CE2

CE3

OE

ZZ

CY7C1485V33–4M × 18

CLK

ADV

ADSC

ADSP

A[21:0]

22

GW

BWE

BW b

BWa

CE1

CE2

CE3

OE

ZZ

PRELIMINARY

MODE

(A[1;0]) 2

BURST Q0

CE COUNTER

CLR

Q1

Q

ADDRESS

19

CE

D

REGISTER

19

D DQd, DPd Q

BYTEWRITE

REGISTERS

D DQc, DPc Q

BYTEWRITE

REGISTERS

D DQb, DPb Q

BYTEWRITE

REGISTERS

D DQa, DPa Q

BYTEWRITE

REGISTERS

D ENABLE CE Q

REGISTER

D ENABLE DELAY Q

REGISTER

SLEEP

CONTROL

MODE

(A[1;0]) 2

BURST Q0

CE COUNTER

CLR

Q1

Q

ADDRESS

20

CE

D

REGISTER

20

D DQb, DPb Q

BYTEWRITE

REGISTERS

D DQa, DPa Q

BYTEWRITE

REGISTERS

D

CE

ENABLE CE

REGISTER

Q

D ENABLE DELAY Q

REGISTER

SLEEP

CONTROL

CY7C1484V33

CY7C1485V33

21

2M × 36

MEMORY

ARRAY

36

36

OUTPUT

REGISTERS

CLK

INPUT

REGISTERS

CLK

DQa,b,c,d

DPa,b,c,d

22

4M × 18

MEMORY

ARRAY

18

18

OUTPUT

REGISTERS

CLK

INPUT

REGISTERS

CLK

DQa,b

DPa,b

Document #: 38-05285 Rev. *A

Page 2 of 29

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