CY7C1484V33-167 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1484V33-167

2M x 36/4M x 18 Pipelined DCD SRAM

Cypress Semiconductor 

PRELIMINARY

CY7C1484V33

CY7C1485V33

Pin Definitions (continued)

Pin Name

BWE

CLK

CE1

CE2

CE3

OE

ADV

ADSP

ADSC

MODE

ZZ

DQa, DPa

DQb, DPb

DQc, DPc

DQd, DPd

DQe, DPe

DQf, DPf

DQg, DPg

DQh, DPh

TDO

TDI

TMS

TCK

VDD

VSS

VDDQ

VSSQ

144M

NC

I/O

Input-

Synchronous

Input-

Clock

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Static

Input-

Asynchronous

I/O-

Synchronous

Pin Description

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

be asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3 to select/deselect the device. (TQFP Only)

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE2 to select/deselect the device. (TQFP Only)

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated,

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

from a deselected state.

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically

increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW,

A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is

deasserted HIGH.

Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW,

A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When

ADSP and ADSC are both asserted, only ADSP is recognized.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation.

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

condition with data integrity preserved.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx

and DPx are placed in a three-state condition.DQ a,b,c,d and h are eight bits wide. DP a,b,c,d

are one bit wide.

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only)

Synchronous

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. (BGA Only)

Synchronous

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous (BGA Only)

JTAG serial clock Serial clock to the JTAG circuit. (BGA Only)

Power Supply Power supply inputs to the core of the device. Should be connected to

3.3 –5%/+5% power supply.

Ground

Ground for the core of the device. Should be connected to ground of the system.

I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375V(min.) to VDD(max.)

I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.

–

NC. This pin is reserved for expansion to 144 Mb.

–

No Connects.

Document #: 38-05285 Rev. *A

Page 6 of 29

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