CS5360 Просмотр технического описания (PDF) - Cirrus Logic
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CS5360 Datasheet PDF : 22 Pages
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CS5360
2. SYSTEM DESIGN
The CS5360 is a 24-bit, 2-channel analog-to-digital
converter designed for digital audio applications.
This device uses two one-bit delta-sigma modula-
tors which simultaneously sample the analog input
signals at 128 times the output sample rate (Fs).
The resulting serial bit streams are digitally fil-
tered, yielding a pair of 24-bit values. This tech-
nique yields nearly ideal conversion performance
independent of input frequency and amplitude. The
converter does not require difficult-to-design or ex-
pensive anti-alias filters and does not require exter-
nal sample-and-hold amplifiers or a voltage
reference. Very few external components are re-
quired to support this ADC. Normal power supply
decoupling components and a resistor and capaci-
tor on each input for anti-aliasing are the only ex-
ternal components required, as shown in Figure 6.
An on-chip voltage reference provides for a differ-
ential input signal range of 2.0 Vrms. Output data
is available in serial form, coded as 2’scomplement,
24-bit numbers. Typical power consumption is
325 mW which can be reduced to 1.0 mW by using
the power-down feature.
2.1 Master Clock
The master clock (MCLK) is the clock source for
the delta-sigma modulator and digital filters. In
Master Mode, the frequency of this clock must be
256x Fs. In SlaveMode, the master clock must be
either 256x, 384x or 512x Fs. Table 1 shows some
common master clock frequencies.
3. SERIAL DATA INTERFACE
The CS5360 supports three serial data formats, in-
cluding I2S, selected via the digital interface format
pins DIF0 and DIF1. The digital interface format de-
termines the relationship between the serial data,
left/right clock and serial clock. Table 2 lists the
three formats and their associated figure number.
The serial data interface is accomplished via the se-
rial data output, SDATA, serial data clock, SCLK,
and the left/right clock, LRCK.
DIF1
0
0
1
1
DIF0
0
1
0
1
FORMAT
0
1
2
power-down
FIGURE
8
9
10
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Table 2. Digital Input Formats
3.1 Serial Data
The serial data block consists of 24 bits of audio
data presented in 2’s-complement format with the
MSB-first followed by 8 Peak Signal Level, PSL,
bits as shown in Figure 7. The data is clocked from
SDATA by the serial clock and the channel is de-
termined by the Left/Right clock.
24 Audio
Data Bits
SDATA 23 22 21 20 19 18
8 PSL Bits
1 0 P7 P6 P1 P0
FRAME
Figure 7. Data Block and Frame
LRCK
(kHz)
32
44.1
48
256 X
8.1920
11.2896
12.2880
MCLK (MHz)
384 X
12.2880
16.9344
18.4320
512 X
16.3840
22.5792
24.5760
Table 1. Common Clock Frequencies
3.2 Serial Clock
The serial clock shifts the digital audio data from the
internal data registers via the SDATA pin. SCLK is
an output in Master Mode. Internal dividers will di-
vide the master clock by 4 to generate a serial clock
which is 64x Fs. In Slave Mode, SCLK is an input
with a serial clock typically between 48x and 96x Fs.
However, the serial clock must be a minimum of 64x
Fs to access the Peak Signal Level bits.
DS280PP2
9
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