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CS5360

24-Bit Stereo A/D Converter for Digital Audio

Cirrus Logic 

CS5360

3.3 Left / Right Clock

The Left/Right clock determines which channel,

left or right, is to be output on SDATA. Although

the outputs for each channel are transmitted at dif-

ferent times, Left/Right pairs represent simulta-

neously sampled analog inputs. In Master Mode,

LRCK is an output whose frequency is equal to Fs.

In Slave Mode, LRCK is an input whose frequency

must be equal to the output sample rate, Fs.

3.4 Master Mode

In Master mode, SCLK and LRCK are outputs

which are internally derived from the Master

Clock. Internal dividers will divide MCLK by 4 to

generate a SCLK which is 64x Fs and by 256 to

generate a LRCK which is equal to Fs. Master

mode is only supported with a 256x master clock.

The CS5360 is placed in the Master mode with a

47 kΩ pull-down resistor on the OVFL pin.

3.5 Slave Mode

LRCK and SCLK become inputs in SLAVE mode.

LRCK must be externally derived from MCLK and

be equal to Fs. The serial clock is typically between

64x and 96x Fs. A 48x Fs serial clock is possible

though will not allow access to the Peak Signal

Level bits. Master clock frequencies of 256x, 384x

and 512x Fs are supported. The ratio of the applied

master clock to the left/right clock is automatically

detected during power-up and internal dividers are

set to generate the appropriate internal clocks.

3.6 Analog Connections

Figure 6 shows the analog input connections. The

analog inputs are presented to the modulators via

the AINR+/- and AINL+/- pins. Each analog input

pin will accept a maximum of 1Vrms centered at

+2.2 Volt as shown in Figure 11. Input signals can

be AC or DC coupled and the CMOUT output may

be used as a reference for DC coupling. However,

CMOUT is not buffered, and the maximum current

is 10 µA.

3.6 V

2.2 V

0.78 V

3.6 V

2.2 V

0.78 V

CS5360

AIN+

AIN-

Full Scale Input level= (AIN+) - (AIN-)= 5.67 Vpp

Figure 11. Full Scale Input Levels

The CS5360 samples the analog inputs at 128x Fs,

6.144MHz for a 48kHz sample-rate. The digital fil-

ter rejects all noise above 26.3kHz except for fre-

quencies right around 6.144MHz ±21.7kHz (and

multiples of 6.144MHz). Most audio signals do not

have significant energy at 6.144MHz. Neverthe-

less, a 150 Ω resistor in series with each analog in-

put and a 2.2 nF capacitor across the inputs will

attenuate any noise energy at 6.144MHz, in addi-

tion to providing the optimum source impedance

for the modulators. The use of capacitors which

have a large voltage coefficient must be avoided

since these will degrade signal linearity. NPO and

COG capacitors are acceptable. If active circuitry

precedes the ADC, it is recommended that the

above RC filter is placed between the active circuit-

ry and the AINR and AINL pins. The above exam-

ple frequencies scale linearly with the sample rate.

3.7 High Pass Filter

The operational amplifiers in the input circuitry

driving the CS5360 may generate a small DC offset

into the A/D converter. The CS5360 includes a

high pass filter after the decimator to remove any

DC offset which could result in recording a DC lev-

el, possibly yielding "clicks" when switching be-

tween devices in a multichannel system. The high

pass filter can be disabled with the HP DEFEAT

pin.

The high pass filter works by continuously sub-

tracting a measure of the dc offset from the output

of the decimation filter. If the HP DEFEAT pin is

DS280PP2

11

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