CS5360 Просмотр технического описания (PDF) - Cirrus Logic
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CS5360 Datasheet PDF : 22 Pages
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CS5360
SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5 V ±5%; Inputs: Logic 0 = 0 V,
Logic 1 = VA+ = VD+; CL = 20 pF)
Parameter
Symbol Min
Typ
Max
Output Sample Rate
MCLK Period
FS
8.0
-
50
MCLK / LRCK = 256 tclkw
78
-
1953
MCLK / LRCK = 384
52
-
1302
MCLK / LRCK = 512
39
-
976
MCLK Low
MCLK / LRCK = 256
tclkl
31
-
-
MCLK / LRCK = 384
20
-
-
MCLK / LRCK = 512
15
-
-
MCLK High
MCLK / LRCK = 256 tclkh
31
-
-
MCLK / LRCK = 384
20
-
-
MCLK / LRCK = 512
15
-
-
Peak Update Pulse Width
Master Mode
pupulse
20
-
-
SCLK Falling to LRCK
SCLK Falling to SDATA Valid
SCLK Duty Cycle
(Note 7) tmslr
-10
-
10
(Note 7) tsdo
-10
-
35
-
50
-
SCLK Falling to Frame Valid
LRCK Edge to OVFL Valid
LRCK Edge to OVFL Edge Delay
Slave Mode
(Note 7)
tsfo
-10
-
Note 8
tovfl
-10
-
30
tovfl
-10
- Note 12
LRCK Duty Cycle
25
50
75
SCLK Period
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Falling to SDATA Valid
LRCK Edge to MSB Valid
SCLK Rising to LRCK Edge Delay
LRCK Edge to Rising SCLK Setup Time
SCLK Falling to Frame Delay
tsclkw
Note 9
-
-
(Note 10) tsclkl
Note 13
-
-
(Note 11) tsclkh
50
-
-
(Note 7)
tdss
-
- Note 13
tlrdss
-
- Note 13
(Note 14) tslr1
50
-
-
(Note 14) tslr2
Note 13
-
-
tsfo
-
- Note 15
Notes: 7.
8.
9.
10.
SCLK Rising for Mode 1
-(--1---0----2---4--1--)--(---F----S----) + 30 ns
-(--9---6----)-1--(--F----S-----)
Pulse Width High for Mode 1
11. Pulse Width Low for Mode 1
12. (---5---1----2---1)---(--F----S-----) + 20 ns
13. (---5---1----2---1)---(--F----S-----) + 50 ns
14. SCLK Falling for Mode 1
15. (---3---8----4---1)---(--F----S-----) + 35 ns
Unit
kHz
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
6
DS280PP2
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