BUK9006-55A Просмотр технического описания (PDF) - Philips Electronics
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BUK9006-55A Datasheet PDF : 10 Pages
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Philips Semiconductors
5. Bare die outline
BUK9006-55A
TrenchMOS™ logic level FET
G
H
D
L
M
N
P−P
Drain connection made to underside.
A
F
B
1
2
P
E
P
TYPICAL DIMENSIONS
UNIT A
B
D
E
F
mm 4.30 4.30 3.36 3.62 0.54
G
H
L
M
0.4 0.096 0.175 0.27
N
0.24
± 0.025
03nn80
Fig 12. Bare die outline.
Table 4: Bare die information
Parameter
Top-side metallization (gate and source
bond pads)
Back-side metallization (drain contact)
Passivation layer
Description
5 µm Al + 1 % Si (sputtered)
0.1 µm Ti / 0.3 µm Ni / 0.1 µm Ag (evaporated)
1 µm Si3N4
9397 750 11571
Preliminary data
Rev. 01 — 1 August 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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