AD73360AR Просмотр технического описания (PDF) - Analog Devices

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AD73360AR

Six-Input Channel Analog Front End

Analog Devices 

AD73360

CONTROL REGISTER D

Table X. Control Register D Description

7

PUI2

6

I2GS2

5

I2GS1

4

I2GS0

3

PUI1

2

I1GS2

1

I1GS1

0

I1GS0

Bit Name

0 I1GS0

1 I1GS1

2 I1GS2

3 PUI1

4 I2GS0

5 I2GS1

6 I2GS2

7 PUI2

Description

ADC1:Input Gain Select (Bit 0)

ADC1:Input Gain Select (Bit 1)

ADC1:Input Gain Select (Bit 2)

Power Control (ADC1); 1 = ON, 0 = OFF

ADC2:Input Gain Select (Bit 0)

ADC2:Input Gain Select (Bit 1)

ADC2:Input Gain Select (Bit 2)

Power Control (ADC2); 1 = ON, 0 = OFF

CONTROL REGISTER E

Table XI. Control Register E Description

7

PUI4

6

I4GS2

5

I4GS1

4

I4GS0

3

PUI3

2

I3GS2

1

I3GS1

0

I3GS0

Bit Name

0 I3GS0

1 I3GS1

2 I3GS2

3 PUI3

4 I4GS0

5 I4GS1

6 I4GS2

7 PUI4

Description

ADC3:Input Gain Select (Bit 0)

ADC3:Input Gain Select (Bit 1)

ADC3:Input Gain Select (Bit 2)

Power Control (ADC3); 1 = ON, 0 = OFF

ADC4:Input Gain Select (Bit 0)

ADC4:Input Gain Select (Bit 1)

ADC4:Input Gain Select (Bit 2)

Power Control (ADC4); 1 = ON, 0 = OFF

CONTROL REGISTER F

Table XII. Control Register F Description

7

PUI6

6

I6GS2

5

I6GS1

4

I6GS0

3

PUI5

2

I5GS2

1

I5GS1

0

I5GS0

Bit Name

0 I5GS0

1 I5GS1

2 I5GS2

3 PUI5

4 I6GS0

5 I6GS1

6 I6GS2

7 PUI6

Description

ADC5:Input Gain Select (Bit 0)

ADC5:Input Gain Select (Bit 1)

ADC5:Input Gain Select (Bit 2)

Power Control (ADC5); 1 = ON, 0 = OFF

ADC6:Input Gain Select (Bit 0)

ADC6:Input Gain Select (Bit 1)

ADC6:Input Gain Select (Bit 2)

Power Control (ADC6); 1 = ON, 0 = OFF

–16–

REV. A

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