AD73360AR Просмотр технического описания (PDF) - Analog Devices

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AD73360AR

Six-Input Channel Analog Front End

Analog Devices 

CONTROL REGISTER A

Table VII. Control Register A Description

7

6

5

4

3

2

RESET DC2

DC1

DC0

SLB

–

AD73360

1

MM

0

DATA/PGM

Bit Name

0 DATA/PGM

1 MM

2 Reserved

3 SLB

4 DC0

5 DC1

6 DC2

7 RESET

Description

Operating Mode (0 = Program; 1 = Data Mode)

Mixed Mode (0 = OFF; 1 = Enabled)

Must Be Programmed to Zero (0)

SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)

Device Count (Bit 0)

Device Count (Bit 1)

Device Count (Bit 2)

Software Reset (0 = OFF; 1 = Initiates Reset)

CONTROL REGISTER B

Table VIII. Control Register B Description

7

CEE

6

MCD2

5

MCD1

4

MCD0

3

SCD1

2

SCD0

1

DR1

0

DR0

Bit Name

0 DR0

1 DR1

2 SCD0

3 SCD1

4 MCD0

5 MCD1

6 MCD2

7 CEE

Description

Decimation Rate (Bit 0)

Decimation Rate (Bit 1)

Serial Clock Divider (Bit 0)

Serial Clock Divider (Bit 1)

Master Clock Divider (Bit 0)

Master Clock Divider (Bit 1)

Master Clock Divider (Bit 2)

Control Echo Enable (0 = OFF; 1 = Enabled)

CONTROL REGISTER C

Table IX. Control Register C Description

7

6

5

4

3

2

5VEN

RU PUREF

–

–

–

1

0

–

GPU

Bit Name

0 GPU

1 Reserved

2 Reserved

3 Reserved

4 Reserved

5 PUREF

6 RU

7 5VEN

Description

Global Power-Up Device (0 = Power Down; 1 = Power Up)

Must Be Programmed to Zero (0)

Must Be Programmed to Zero (0)

Must Be Programmed to Zero (0)

Must Be Programmed to Zero (0)

REF Power (0 = Power Down; 1 = Power Up)

REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)

Enable 5 V Operating Mode (0 = Disable 5 V Mode;

1 = Enable 5 V Mode)

REV. A

–15–

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