74F193 Просмотр технического описания (PDF) - Philips Electronics

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74F193

Up/down binary counter with separate up/down clocks

Philips Electronics 

Philips Semiconductors

Up/down binary counter with separate up/down clocks

Product specification

74F193

Timing Diagram (Typical clear, load, and count sequence)

CLEAR1 MR

LOAD

PL

D0

D1

DATA

D2

D3

COUNT UP2 CPU

COUNT DOWN2

CPD

Q0

Q1

OUTPUTS

Q2

Q3

TCU

TCD

SEQUENCE

0

13

14 15 0 1 2

COUNT UP

NOTES:

CLEAR PRESET

1. Clear overrides load, data, and count inputs.

2. When counting up, count-down input must be High; when counting down, count-up input must be High.

Binary Counter

1 0 15 14 13

COUNT DOWN

SF00756

TEST CIRCUIT AND WAVEFORMS

VIN

PULSE

GENERATOR

VCC

VOUT

D.U.T.

NEGATIVE

PULSE

90%

tw

VM

10%

tTHL (tf )

VM

10%

tTLH (tr )

90%

AMP (V)

0V

RT

CL RL

Test Circuit for Totem-Pole Outputs

POSITIVE

PULSE

10%

tTLH (tr )

90%

VM

tw

tTHL (tf )

90%

VM

AMP (V)

10%

0V

DEFINITIONS:

RL = Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.

CL = Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT of

pulse generators.

Input Pulse Definition

family

74F

INPUT PULSE REQUIREMENTS

amplitude VM rep. rate

tw

tTLH

3.0V 1.5V 1MHz 500ns 2.5ns

tTHL

2.5ns

SF00006

1995 Jul 17

8

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