XRT7302IV Просмотр технического описания (PDF) - Exar Corporation

Номер в каталоге

Компоненты Описание

Список матч

XRT7302IV

2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation 

áç

2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT7302

TABLE OF CONTENTS

REV. 1.1.6

General description ........................................................................................................... 1

FEATURES ................................................................................................................................................ 1

APPLICATIONS ......................................................................................................................................... 1

XRT7302 BLOCK DIAGRAM ..................................................................................................................... 1

TRANSMIT INTERFACE CHARACTERISTICS ........................................................................................ 2

RECEIVE INTERFACE CHARACTERISTICS ........................................................................................... 2

PIN OUT OF THE XRT7302 ...................................................................................................................... 2

................................................................................. TABLE OF CONTENTS I

Pin descriptions ................................................................................................................. 3

ELECTRICAL CHARACTERISTICS ................................................................................. 14

ABSOLUTE MAXIMUM RATINGS ................................................................................................... 14

Figure 1.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel shown) ...... 16

Figure 2.Timing Diagram of the Transmit Terminal Input Interface ................................................................ 16

Figure 3.Timing Diagram of the Receive Terminal Output Interface .............................................................. 16

Figure 4.Microprocessor Serial Interface Data Structure ............................................................................... 20

Figure 5.Timing Diagram for the Microprocessor Serial Interface .................................................................. 21

SYSTEM DESCRIPTION ................................................................................................... 22

THE TRANSMIT SECTION - CHANNELS 0 AND 1 ................................................................................ 22

THE RECEIVE SECTION - CHANNELS 0 AND 1 ................................................................................... 22

THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 22

Table 1:Role of Microprocessor Serial Interface pins when the XRT7302 is operating in the Hardware Mode ..

22

Figure 6.Functional Block Diagram of the XRT7302 ...................................................................................... 23

1.0 SELECTING THE DATA RATE ......................................................................................................... 23

1.1 CONFIGURING CHANNEL(N) ............................................................................................................ 23

Table 2:Addresses and Bit Formats of XRT7302 Command Registers ......................................................... 24

Table 3:Selecting the Data Rate for Channel(n) of the XRT7302, via the E3_Ch(n) and STS-1/DS3_Ch(n) input

pins (Hardware Mode) ....................................................................................................................... 24

COMMAND REGISTER CR4-(N) .................................................................................................... 25

Table 4:Selecting the Data Rate for Channel(n) of the XRT7302 via the STS-1/DS3_Ch(n) and the E3_Ch(n)

bit-fields in the Appropriate Command Register (HOST Mode) ........................................................ 25

2.0 THE TRANSMIT SECTION ............................................................................................................... 25

2.1 THE TRANSMIT LOGIC BLOCK ......................................................................................................... 25

Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 25

Figure 7. The typical interface for Data Transmission in Dual-Rail Format from the Transmitting Terminal Equip-

ment to the Transmit Section of a channel of the XRT7302 ............................................................. 26

Figure 8.How the XRT7302 Samples the data on the TPData and TNData input pins .................................. 26

Configure Channel(n) to accept Single-Rail Data from the Terminal Equipment .............................. 26

COMMAND REGISTER CR1-(N) ..................................................................................................... 26

Figure 9.The Behavior of the TPData and TxClk Input Signals while the Transmit Logic Block is Accepting Sin-

gle-Rail Data from the Terminal Equipment ..................................................................................... 27

2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................. 27

2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................... 27

B3ZS Encoding .................................................................................................................................. 27

I

Share Link: