XRT7302IV Просмотр технического описания (PDF) - Exar Corporation
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XRT7302IV Datasheet PDF : 62 Pages
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XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.1.6
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
• Integrated Pulse Shaping Circuit
• Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
• Contains Transmit Clock Duty Cycle Correction Cir-
cuit on-chip
• Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
• Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
• Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
• Transmitter can be turned off in order to support
redundancy designs
PIN OUT OF THE XRT7302
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization
(Optional) and Timing Recovery
• Declares and Clears the LOS alarm per ITU-T
G.775 requirements for E3 and DS3 applications
• Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
• Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
• Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
• Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
• Recovered Data can be automatically muted while
the LOS Condition is declared
• Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
• Receiver can be powered down in order to con-
serve power in redundancy designs
TxLEV0
1
TAOS0
2
DVDD
3
DMO0
4
DGND
5
AGND
6
DVDD
7
Host/(HW)
8
RxClk0
9
RNEG0
10
RPOS0
11
DGND
12
RLOS0
13
LCV0
14
RLOL0
15
EXClk0
16
CS/(ENDECDIS)
17
SClk/(RxOff1)
18
SDI/(RxOff0)
19
SDO/(E3_Ch0)
20
80 Lead TQFP
60
TxLEV1
59
TAOS1
58
DVDD
57
DMO1
56
DGND
55
AGND
54
DVDD
53
LOSMUTEN
52
RxClk1
51
RNEG1
50
RPOS1
49
DGND
48
RLOS1
47
LCV1
46
RLOL1
45
EXClk1
44
VDD
43
GND
42
REGR/(RxClkINV)
41
STS-1/DS3_Ch1
2
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