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XRT7302IV

2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation 

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XRT7302

SEPTEMBER 2000

2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 1.1.6

GENERAL DESCRIPTION

The XRT7302 Dual Channel E3/DS3/STS-1 Trans-

ceiver IC consists of two fully integrated transmitter

and receiver line transceivers designed for E3, DS3

or SONET STS-1 applications.

Each channel can be configured to support the E3

(34.368 Mbps), DS3 (44.736 Mbps) or the SONET

STS-1 (51.84 Mbps) rates. Each channel can be con-

figured to operate in a mode/data rate that is indepen-

dent of the other channel.

In the transmit direction, each channel in the

XRT7302 encodes input data to either B3ZS or HDB3

format and converts the data into the appropriate

pulse shapes for transmission over coaxial cable via a

1:1 transformer.

In the receive direction, the XRT7302 can perform

Equalization on incoming signals, perform Clock Re-

covery, decode data from either B3ZS or HDB3 for-

mat, convert the receive data into TTL/CMOS format,

check for LOS or LOL conditions and detect and de-

clare the occurrence of Line Code Violations.

FEATURES

• Meets E3/DS3/STS-1 Jitter Tolerance Require-

ments

• Contains a 4-Wire Microprocessor Serial Interface

• Full Loop-back Capability

• Transmit and Receive Power Down Modes

• Full Redundancy Support

• Single +5V Power Supply

• Uses Minimum External components

• Operates over -40°C to +85°C Temperature Range

• Available in an 80 pin TQFP Thermal Enhanced

package with integral Heat Sink

APPLICATIONS

• Digital Cross Connect Systems

• CSU/DSU Equipment

• Routers

• Fiber Optic Terminals

• Multiplexers

• ATM Switches

XRT7302 BLOCK DIAGRAM

E3_Ch(n) STS-1/DS3_Ch(n) Host/HW

RLOL(n) ExClk(n)

RxClkINV

RTIP(n)

RRing(n)

REQEN(n)

RxOFF(n)

LOSTHR(n)

SDI

SDO

SClk

CS

REGR

TTIP(n)

TRing(n)

MTIP(n)

MRing(n)

DMO(n)

AGC/

Equalizer

Slicer

Clock

Recovery

Peak Detector

LOS Detector

Data

Recovery

Serial

Processor

Interface

Loop MUX

Invert

HDB3/

B3ZS

Decoder

Device

Monitor

Pulse

Shaping

Tx

Control

HDB3/

B3ZS

Encoder

Transmit

Logic

Duty Cycle Adjust

Channel 0

RxClk(n)

RPOS(n)

RNEG(n)

LCV(n)

ENDECDIS

RLOS(n)

LLB(n)

RLB(n)

TAOS(n)

TPData(n)

TNData(n)

TxClk(n)

TxLEV(n)

TxOFF(n)

Channel 1

Notes: 1. (n) = 0 or 1 for the respective channel.

2. Serial Processor Interface pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode.

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

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