GD25Q20 Просмотр технического описания (PDF) - Unspecified
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GD25Q20 Datasheet PDF : 38 Pages
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5. DATA PROTECTION
The GD25Q20B provides the following data protection methods:
� Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
� Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
� Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0 bit.
� DPoeweperP-DoowweUnr-DMnoowidfneoMcroommdme:SaInnedD.ceteop rPower-Down Mode, all commands are ignored except the Release from Deep
Dual and Quad Serial Flash
GD25Q40B/20B
Table1. GD25Q20B Protected area size (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0 Blocks
Addresses
Density
0
X
X
0
0
NONE
0
0
X
0
1
3
NONE
030000H-03FFFFH
NONE
64KB
0
0
X
1
0
2 and 3
020000H-03FFFFH
128KB
0
1
X
0
1
0
000000H-00FFFFH
64KB
0
1
X
1
0
0 and 1
000000H-01FFFFH
128KB
0
X
X
1
1
0 to 3
000000H-03FFFFH
256KB
1
X
0
0
0
NONE
1
0
0
0
1
3
NONE
03F000H-03FFFFH
NONE
4KB
1
0
0
1
0
3
03E000H-03FFFFH
8KB
1
0
0
1
1
3
03C000H-03FFFFH
16KB
1
0
1
0
X
3
038000H-03FFFFH
32KB
1
0
1
1
0
3
038000H-03FFFFH
32KB
1
1
0
0
1
0
000000H-000FFFH
4KB
1
1
0
1
0
0
000000H-001FFFH
8KB
1
1
0
1
1
0
000000H-003FFFH
16KB
1
1
1
0
X
0
000000H-007FFFH
32KB
1
1
1
1
0
0
000000H-007FFFH
32KB
1
X
1
1
1
0 to 3
000000H-03FFFFH
256KB
Portion
NONE
Upper 1/4
Upper 1/2
Lower 1/4
Lower 1/2
ALL
NONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/8
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/8
ALL
10
38 - 9
Rev.1.1
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