MBM29DL321BD Просмотр технического описания (PDF) - Fujitsu

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MBM29DL321BD

32M (4M ×8/2M ×16) BIT Dual Operation

Fujitsu 

MBM29DL32XTD/BD-80/90/12

2. AC Characteristics

• Read Only Operations Characteristics

Parameter

symbols

JEDEC Standard

Description

Test setup

80

(Note)

90

(Note)

12

(Note)

Unit

tAVAV

tAVQV

tELQV

tGLQV

tEHQZ

tGHQZ

tAXQX

tRC Read Cycle Time

— Min. 80

tACC Address to Output Delay

CE = VIL

OE = VIL

Max.

80

tCE Chip Enable to Output Delay

OE = VIL Max. 80

tOE Output Enable to Output Delay

— Max. 30

tDF Chip Enable to Output High-Z

— Max. 25

tDF Output Enable to Output High-Z

— Max. 25

tOH

Output Hold Time from Addresses,

CE or OE, Whichever Occurs First

— Min. 0

90

120 ns

90

120 ns

90

120 ns

35

50 ns

30

30 ns

30

30 ns

0

0

ns

—

tREADY RESET Pin Low to Read Mode

— Max. 20

20

20

µs

—

tELFL

tELFH

CE or BYTE Switching Low or High

— Max.

5

5

5

ns

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (MBM29DL32XTD/BD 80)

1 TTL gate and 100 pF (MBM29DL32XTD/BD 90/12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output:1.5 V

Device

Under

Test

CL

3.3 V

IN3064

or Equivalent

2.7 kΩ

6.2 kΩ

Diodes = IN3064

or Equivalent

Figure 4 Test Conditions

14

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