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ACT-D1M96S

High Speed Multichip Module 96 MegaBit 3.3V Synchronous DRAM

Aeroflex Corporation 

Operation

All inputs to the ACT-D1M96S SDRAM are

latched on the rising edge of the system

(synchronous) clock. The outputs, DQ0-DQ95,

also are referenced to the rising edge of CLK.

The ACT-D1M96S has two banks in each section

that are accessed independently. A bank must

be activated before it can be accessed (read from

or written to). Refresh cycles refresh both banks

alternately.

Five basic commands or functions control most

operations of the ACT-D1M96S:

G Bank activate/row-address entry

G Column-address entry/write operation

G Column-address entry/read operation

G Bank deactivate

G Auto-refresh

Additionally, operations can be controlled by

three methods:

G Chip select (CS) to select/ deselect the

devices

G DQMx to enable/mask the DQ signals on a

cycle-by-cycle basis

G CKE to suspend (or gate) the CLK input

The device contains a mode register that must

be programmed for proper operation. Table 1

through Table 3 show the various operations that

are available on the ACT-D1M96S. These truth

tables identify the command and/or operations

and their respective mnemonics. Each truth table

is followed by a legend that explains the

abbreviated symbols. An access operation refers

to any read or write command in progress at cycle

n. Access operations include the cycle upon

which the read or write command is entered and

all subsequent cycles through the completion of

the access burst.

Burst Sequence

All data for the ACT-D1M96S is written or read in

a burst fashion, that is, a single starting address

is entered into the device and then the

ACT-D1M96S internally accesses a sequence of

locations based on that starting address. After

the first access some of the subsequent

accesses can be at preceding as well as

succeeding column addresses, depending on

the starting address entered. This sequence is

programmed to follow a serial burst (see Table 4

and 5). The length of the burst can be

programmed is 4 or 8. After a read burst is

complete (as determined by the

programmed-burst length), the outputs are in the

high-impedance state until the next read access

is initiated.

Latency

The beginning data-out cycle of a read burst can

be programmed to occur two CLK cycles after the

read command. The delay between the READ

command and the beginning of the output burst

is known as CAS latency. After the initial output

cycle begins, the data burst occurs at the CLK

frequency without any intervening gaps.

There is no latency for data-in cycles (write

latency). The first data-in cycle of a write burst is

entered at the same rising edge of CLK on which

the WRT command is entered. The write latency

is fixed and is not determined by the

mode-register contents.

Two-Bank Operation

The ACT-D1M96S contains two independent

banks that can be accessed individually or in an

interleaved fashion. Each bank must be activated

with a row address before it can be accessed.

Each bank then must be deactivated before it can

be activated again with a new row address. The

bank-activate/row-address-entry command

(ACTV) is entered by holding RAS low, CAS high,

WE high, and A11 valid on the rising edge of CLK.

A bank can be deactivated either automatically

during a READ-P or a WRT-P command or by

use of the deactivate-bank (DEAC) command.

Both banks can be deactivated at once by use of

the DCAB command (see Table 1 and the section

on bank deactivation).

Two-Bank Row-Access Operation

The two-bank feature allows access of

information on random rows at a higher rate of

operation than is possible with a standard DRAM,

by activating one bank with a row address and,

while the data stream is being accessed to/from

that bank, activating the second bank with

another row address. When the data stream to

or from the first bank is complete, the data stream

to or from the second bank can begin without

interruption. After the second bank is activated,

the first bank can be deactivated to allow the

entry of a new row address for the next round of

accesses. In this manner, operation can continue

in an interleaved fashion.

Aeroflex Circuit Technology

2

SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700

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