ACT-D1M96S Просмотр технического описания (PDF) - Aeroflex Corporation
Номер в каталоге
Компоненты Описание
Список матч
ACT-D1M96S Datasheet PDF : 14 Pages
| |||
ACT-D1M96S High Speed
96 MegaBit 3.3V Synchronous DRAM
Multichip Module
Features
I 6 Low Power Micron 1M X 16 Synchronous Dynamic
Random Access Memory Chips in one MCM
I User Configureable as "2" Independent 512K X 48 X 2
Banks
I High-Speed, Low-Noise, Low-Voltage TTL (LVTTL)
Interface
I 3.3-V Power Supply (±10% Tolerance)
I Separate Logic and Output Driver Power Pins
I Two Banks for On-Chip Interleaving (Gapless
Accesses)
I Up to 50-MHz Data Rates
I CAS Latency (CL) Programmable to 2 Cycles From
Column-Address Entry
I Burst Length Programmable to 4 or 8
I Pipeline Architecture
I Cycle-by-Cycle DQ-Bus Write Mask Capability With
Upper and Lower Byte Control
I Chip Select and Clock Enable for Enhanced-System
Interfacing
I Serial Burst Sequence
I Auto-Refresh
I 4K Refresh (Total for Both Banks)
I 200-lead CQFP, cavity-up package
General Description
The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM)
organized as 2 independent 512K X 48 X 2 banks. All inputs and outputs of the ACT-D1M96S are compatible
with the LVTTL interface. All inputs and outputs are synchronized with the CLK input to simplify system design
and enhance use with high-speed microprocessors and caches.
BLOCK DIAGRAM
CS1
CLK1
S
CKE1
E
DQMU1
C
DQML1
T
RAS1
CAS1
I
WE1
O
A0-A11
12
N
A
BANK T
BANK B
CS2
CLK2
S
CKE2
E
DQMU2
DQML2
C
RAS2
T
CAS2
I
WE2
O BA0-BA11
12
N
B
BANK T
BANK B
1M X 16 or
512K X 16 X 2 Banks
16
DQ0-15
1M X 16 or
512K X 16 X 2 Banks
16
DQ48-63
1M X 16 or
512K X 16 X 2 Banks
16
DQ16-31
1M X 16 or
512K X 16 X 2 Banks
16
DQ64-79
1M X 16 or
512K X 16 X 2 Banks
16
DQ32-47
1M X 16 or
512K X 16 X 2 Banks
16
DQ80-95
eroflex Circuit Technology - Advanced Multichip Modules © SCD3369-1 REV C 5/31/00
Share Link: 