VPC3211C Просмотр технического описания (PDF) - Micronas
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VPC3211C Datasheet PDF : 48 Pages
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PRELIMINARY DATA SHEET
VPC 3205C, VPC 3215C
I2C Sub- Number Mode
address of bits
h’20 8
w/r
h’30 8
w/r
h’23 8
w/r
h’24 8
w/r
Sync Generator
h’21 16
w/r
h’26 16
w/r
h’27 16
w/r
Function
Default Name
SYNC GENERATOR CONTROL:
bit[1:0] 00
AVO and active Y/C data at same time
01
AVO precedes Y/C data one clock cycle
10
AVO precedes Y/C data two clock cycles
11
AVO precedes Y/C data three clock cycles
bit[2] 0/1
positive/negative polarity for HS signal
bit[3] 0/1
positive/negative polarity for HC signal
bit[4] 0/1
positive/negative polarity for AVO signal
bit[5] 0/1
positive/negative polarity for VS signal
bit[6] 0/1
positive/negative polarity for HELP signal
bit[7] 0/1
positive/negative polarity for INTLC signal
V-SYNC DELAY CONTROL:
bit[7:0]
VS delay (8 LLC clock cycles per LSB)
Priority Bus
priority bus overwrite register
bit [7:0]
8 bit mask, bit[x] = 1 : overwrite priority x
priority bus ID register and control
bit [2:0] 0..7
priority ID, 0 highest
bit [4:3] 0..3
pad driver strength, 0 (strong) to 3 (weak)
bit [5] 0/1
output mode: DIGIT3000/LLC
bit [6] 0/1
source for prio request: AVO/active always
bit [7] 0/1
disable/enable priority interface, if disabled
data pins are tristate !
SYNCMODE
0 AVOPRE
0 HSINV
0 HCINV
0 AVOINV
0 VSINV
0 HELPINV
0 INTLCINV
VSDEL
0 VSDEL
0 PRIOVR
PRIOMODE
0 PID
0 PRIOSTR
0 OMODE
0 PIDSRC
0 PIDE
LINE LENGTH:
bit[10:0]
bit[15:11]
HC START:
bit[10:0]
bit[15:11]
HC STOP:
bit[10:0]
bit[15:11]
LINE LENGTH register
In LLC mode, this register defines the
cycle of the sync counter which generates
the SYNC pulses.
In LLC mode, the synccounter counts from
0 to LINE LENGTH, so this register has to
be set to “number of pixels per line –1”.
In DIGIT3000 mode, LINE LENGTH has to
be set to 1295 for correct adjustment of
vertical signals.
reserved (set to 0)
HC START defines the beginning of the
HC signal in respect to the value of the
sync counter.
reserved (set to 0)
HC STOP defines the end of the HC signal
in respect to the value of the sync counter.
reserved (set to 0)
1295 LINLEN
50 HCSTRT
800 HCSTOP
Micronas
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