VPC3211C Просмотр технического описания (PDF) - Micronas
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VPC3211C Datasheet PDF : 48 Pages
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PRELIMINARY DATA SHEET
VPC 3205C, VPC 3215C
3. Serial Interface
3.1. I2C-Bus Interface
Communication between the VPC and the external
controller is done via I2C-bus. The VPC has an
I2C-bus slave interface and uses I2C clock synchroni-
zation to slow down the interface if required. The
I2C-bus interface uses one level of subaddress: one
I2C-bus address is used to address the IC and a sub-
address selects one of the internal registers. The
I2C-bus chip address is given below:
A6 A5 A4 A3 A2 A1 A0 R/W
1 0 0 0 1 1 1 1/0
The registers of the VPC have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
Figure 3–1 shows I2C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
3.2. Control and Status Registers
Table 3–1 gives definitions of the VPC control and sta-
tus registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read opera-
tions. Write registers that can be read back are indi-
cated in Table 3–1.
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 3–2.
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 3–1.
The register modes given in Table 3–1 are
– w: write only register
– w/r: write/read data register
– r: read data from VPC
– v: register is latched with vertical sync
The mnemonics used in the Intermetall VPC demo
software are given in the last column.
S 1000 111 W Ack
S 1000 111 W Ack
0111 1100
0111 1100
Ack 1 or 2 byte Data
P
Ack S
1000 111
R Ack high byte Data Ack
low byte Data Nak P
I2C write access
subaddress 7c
I2C read access
subaddress 7c
SDA
1
0
S
SCL
Fig. 3–1: I2C-bus protocols
Micronas
W
=0
R
=1
P
Ack = 0
Nak = 1
S
= Start
P
= Stop
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