VPC3211C Просмотр технического описания (PDF) - Micronas

Номер в каталоге

Компоненты Описание

Список матч

VPC3211C

VPC3205C, VPC3215C Video Processor Family

Micronas 

VPC 3205C, VPC 3215C

PRELIMINARY DATA SHEET

2.6.2. Sync Signals

The front end will provide a number of sync/control sig-

nals which are output with the output clock. The sync

signals are generated in the line-locked clock block.

– Href :

horizontal sync

– AVO:

active video out (programmable)

– HC:

horizontal clamp (programmable)

– Vref :

vertical sync

– INTLC:

interlace

– HELPER: PAL+ helper lines

All horizontal signals are not qualified with field infor-

mation, i.e. the signals are present on all lines. The

horizontal timing is shown in Fig. 2–10. Details of the

horizontal/vertical timing are given in Fig. 2–14.

2.6.3. DIGIT3000 Output Format

The picture bus format between all DIGIT3000 ICs is

4:2:2 YCrCb with 20.25 MHz samples/s. Only active

video is transferred, synchronized by the system main

sync signal (MSY) which indicates the start of valid

data for each scan line and which initializes the color

multiplex. The video data is orthogonally sampled

YCrCb, the output format is given in Table 2–2. The

number of active samples per line is 1080 for all stan-

dards (525 and 625).

The output can be switched to 4:1:1 mode with the out-

put format according to Table 2–3.

Via the MSY line, serial data is transferred which con-

tains information about the main picture such as cur-

rent line number, odd/even field etc.). It is generated

by the deflection circuitry and represents the orthogo-

nal timebase for the entire system.

Table 2–2: Orthogonal 4:2:2 output format

Luma Y1

Y2

Chroma Cb1

Cr1

Y3

Y4

Cb3

Cr3

2.6.5. Line-Locked 4:1:1 Output Format

The orthogonal 4:1:1 output format is compatible to the

industry standard. The YCrCb samples are skew-cor-

rected and interpolated to an orthogonal sampling ras-

ter (see Table 2–3).

Table 2–3: 4:1:1 Orthogonal output format

Luma

Chroma

C3, C7

C2, C6

C1, C5

C0, C4

Y1

Cb17

Cb16

Cr17

Cr16

Y2

Cb15

Cb14

Cr15

Cr14

Y3

Cb13

Cb12

Cr13

Cr12

Y4

Cb11

Cb10

Cr11

Cr10

note: C*xY (x = pixel number and y = bit number)

2.6.6. Output Code Levels

Output Code Levels correspond to ITU-R code levels:

Y = 16...240

Black Level = 16

CrCb = 128±112

An overview over the output code levels is given in

Table 2–4.

2.6.7. Output Signal Levels

All data and sync lines operate at TTL compliant lev-

els. With an optional external 3.3 V supply for the out-

put pins, reduced voltage swings can be obtained.

2.6.8. Test Pattern Generator

The YCrCb outputs can be switched to a test mode

where YCrCb data are generated digitally in the

VPC32xx. Test patterns include luma/chroma ramps,

flat field, and a pseudo color bar.

2.6.4. Line-Locked 4:2:2 Output Format

In line-locked mode, the VPC 32xx will produce the

industry standard pixel stream for YCrCb data. The dif-

ference to DIGIT3000 native mode is only the number

of active samples, which of course, depends on the

chosen scaling factor. Thus, Table 2–2 is valid for both

4:2:2 modes.

12

Micronas

Share Link: