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T7264

U-Interface 2B1Q Transceiver

Agere -> LSI Corporation 

Data Sheet

April 1998

T7264 U-Interface 2B1Q Transceiver

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pin Symbol Type

Name/Function

13,

NC

14, 15

— No Connect. These pins are connected to internal nodes of the device. Make no con-

nection to them.

16 OSYNC O Out of Sync (Active-Low). Indicates that framing on the loop signal has not been ac-

quired (or has been lost). Equivalent to the K2 interface oof bit in the DS octet. Can sink

or source 1.6 mA to drive a low-current external LED. Clocked out on the rising edge

of C.

18 VDDO P/I +5 V Supply for the Crystal Oscillator. Ground when driving MCLK with an external

15.36 MHz clock.

19 GNDO P Ground Supply for Oscillator.

20

X1

I Connection #1 for a 15.36 MHz Crystal.

21

X2

I Connection #2 for a 15.36 MHz Crystal.

23 CKOUT O Clock Output. See Table 3.

24 MCLK I Master Clock. See Table 3.

25 CKSEL I Clock Select. See Table 3.

26 HIGHZ I High Impedance (Active-Low). Causes all digital outputs to become 3-stated.

28 VCM — Common-Mode Voltage Reference for the Analog Circuits. Connect via a 0.1 µF

capacitor to GNDA as close to this pin and pin 34 as possible.

29

VRP

— Positive Voltage Reference for the Analog Circuits. Connect via a 0.1 µF capacitor

to GNDA as close to this pin and pin 34 as possible.

30 VRN — Negative Voltage Reference for the Analog Circuits. Connect via a 0.1 µF capacitor

to GNDA as close to this pin and pin 34 as possible.

31

HN

I Hybrid Network Connection, Negative Side. Connect directly to the negative side of

the transformer.

32

LOP

O Line Driver Output Terminal, Positive Side. Connect to the positive side of the trans-

former.

33,

VDDA

39, 42

P +5 V Supply for Analog Circuits.

34, GNDA

40, 41

P Ground Supply for Analog Circuits.

35

LON

O Line Driver Output Terminal, Negative Side. Connect to the negative side of the

transformer.

36

HP

I Hybrid Network Connection, Positive Side. Connect directly to the positive side of

the transformer.

37 SDINN

I Sigma-Delta A/D Converter Input, Negative Side. Connect via an 820 pF ± 5%

capacitor to SDNIP.

38 SDINP

I Sigma-Delta A/D Converter Input, Positive Side. Connect via an 820 pF ± 5%

capacitor to SDNIN.

43 RCLKEN O 80 kHz Receive Baud Clock. Defines receive baud period (rising edge to rising edge).

Lucent Technologies Inc.

5

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