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T7264

U-Interface 2B1Q Transceiver

Agere -> LSI Corporation 

Data Sheet

April 1998

T7264 U-Interface 2B1Q Transceiver

K2 Interface Description

The K2 interface consists of five pins on the T7264: the

data out (DO), data in (DI), data clock (C), K2 frame

sync (F), and master timing clock (MTC). C is a 512 kHz

output signal for clocking data into and out of the device

with 1 bit per clock cycle. F is an 8 kHz signal indicating

the beginning of a K2 frame. MTC is used in LT mode

and must be an 8 kHz ± 32 ppm system clock to meet

T1.601 requirements.

In LT mode, F is phase-locked to the MTC input through

the on-chip digital phase-locked loop. Jitter in MTC is

tracked by F at frequencies below 0.5 Hz. MTC jitter at

frequencies higher than 0.5 Hz is attenuated by the

phase-locked loop (PLL). In the NT mode, the F clock is

derived from incoming data from the U loop.

The first bit of a K2 frame begins simultaneously with

the rising edge of F. Transitions on DO occur following

the rising edge of C, and DI is latched on the falling

edge of C. Figure 8 shows the relationship between the

C, F, DO, and DI.

The K2 frame consists of eight octets for a total of

64 bits. These bits are transferred synchronously over

a 512 kHz interface with a frame rate of 8 kHz or 125 µs.

The major purpose of the K2 interface is to provide

2B+D data transfer between other devices and the chip.

In addition, there are framing bits (DF), U-interface

maintenance and control bits (UM), and device

control/status bits (DC/DS).

B1 TIME SLOT

C

F

DO

1

2

3

4

5

6

7

8

DI

1

2

3

4

5

6

7

8

Figure 8. K2 Interface Timing

5-5167F

C

F

DO

B1

B2

DI

B1

B2

DF

All 1s

UM1

UM2

UM3

DS

D

All 1s

UM1

UM2

UM3

DC

Figure 9. K2 Octets

5-5158

Lucent Technologies Inc.

11

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