CL-PS7500FE-QC-A Просмотр технического описания (PDF) - Cirrus Logic

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CL-PS7500FE-QC-A

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

2.1 CL-PS7500FE Pin Descriptions (cont.)

Name

RESET

nRESET

nROMCS

I_OCLK

MEMCLK

Type

Drive

Strength

Description

OCZ

2 RESET OUTPUT: This is the synchronized version of internal sys-

tem reset signal.

CSOD

2 RESET: This is an open-drain output and a ‘soft’ reset input. This pin

is sampled every 1µs for reset events, so to guarantee a successful

reset, a reset pulse applied to this pin must be longer than 1µs (1µs,

assuming the internal I/O clock is 32 MHz).

OCZ

1 ROM CHIP SELECT: This signal goes low to indicate a ROM

access.

IC

I/O SYSTEM CLOCK: This clock input should always be 32 MHz

when in Divide-by-1 mode, and 64 MHz in Divide-by-2 mode.

IC

MEMORY SYSTEM CLOCK: In synchronous mode, the ARM pro-

cessor FCLK is also driven from this clock.

CPUCLK [MHz] MEMCLK [MHz]

Low

40

40

56

40

64

Low

56

56

64

SnA

High

Low

Low

High

Low

Notes

Recommended

CPUCLK

BD[15:0]

MSCLK

MSDATA

KBCLK

KBDATA

nPOR

IC

BTZ

TOD

TOD

TOD

TOD

ICS

This clock creates FCLK for the ARM CPU in asynchronous mode.

When SnA is high, this signal should be permanently tied high or

low.

2 This is the main external 16-bit I/O bus.

2 MOUSE CLOCK: An open-drain pin for the mouse PS/2 interface.

2 MOUSE DATA: An open-drain pin for the mouse PS/2 interface.

2 KEYBOARD CLOCK: An open-drain pin for the keyboard PS/2

interface.

2 KEYBOARD DATA: An open-drain pin for the keyboard PS/2 inter-

face.

POWER ON RESET: Any low transitions on this pin are detected

and stretched to ensure a full reset.

18

PIN DESCRIPTIONS

ADVANCE DATA BOOK v2.0

June 1997

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