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CL-PS7500FE-QC-A

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

2.1 CL-PS7500FE Pin Descriptions (cont.)

Name

Type

Drive

Strength

Description

VIREF

IA

VIDEO REFERENCE CURRENT: The video DACs need a refer-

ence current to calibrate them. A constant current source is recom-

mended, although a resistor up to VDD is sufficient for many

applications. This current also generates the constant source for the

A-to-D comparators.

VSYNC

OCZ

3 VERTICAL SYNCHRONIZATION: Dependent on the state of bits

19 and 18 in the external register, either a vertical or a composite

(XNOR) sync can be output on this pin, in either polarity. The width

of the VSYNC pulse can be defined in units of a raster.

WS

OCZ

2 WORD SELECT: This signal denotes whether the output serial data

is for the left-hand or right-hand stereo channel.

nTEST

IT

TEST MODE INPUT: This pin should be held permanently high. It

is only intended to be used during production test of the

CL-PS7500FE. An on-chip pull-up resistor is included, but it is

advised to apply an external pull-up resistor to this pin.

nWE

OCZ

2 WRITE ENABLE: This is a active-low signal.

RA[11:0]

OCZ

2 DRAM ROW/COLUMN MULTIPLEXED ADDRESS BUS:

Addresses for this bus are decoded from the ARM processor

address for normal memory accesses, and are generated by the

DMA controller for DMA.

nRAS[3:0]

OCZ

3 DRAM ROW ADDRESS STROBES: Each of these selects one of

the four banks of DRAM available.

nCAS[3:0]

OCZ

3 DRAM COLUMN ADDRESS STROBES: These select the byte

within the word for DRAM accesses.

ATOD[3:0]

IAOD

ANALOG-TO-DIGITAL: These are the four A-to-D channel input

voltages.

ATODREF

IA

ANALOG-TO-DIGITAL REFERENCE: This is the reference voltage

for the A-to-D converter comparators.

OSCPOWER OCZ

1 OCILLATOR POWER: This is the enable signal for the system oscil-

lator(s). When low, this signal can be used to disable the external

oscillator(s).

OSCDELAY CSOD

1 OCILLATOR DELAY: This signal requires an RC network to gener-

ate a fixed delay when restarting the system oscillator(s) on exit

from STOP mode.

June 1997

ADVANCE DATA BOOK v2.0

17

PIN DESCRIPTIONS

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