CL-PS7500FE-QC-A Просмотр технического описания (PDF) - Cirrus Logic

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CL-PS7500FE-QC-A

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Appendixes

A. INITIALIZATION AND BOOT SEQUENCE ........................................................................227

1.

Introduction ..................................................................................................................................... 227

2.

Sample Boot Sequence..................................................................................................................227

3.

Other Methods................................................................................................................................228

B. DUAL-PANEL LIQUID CRYSTAL DISPLAYS...................................................................229

1.

Programming the Video Subsystem ...............................................................................................229

2.

Configuring DMA within the CL-PS7500FE....................................................................................230

3.

Cursor ............................................................................................................................................. 230

4.

Video Frame Buffer Restrictions.....................................................................................................231

C. USING ASTCR AT HIGH MEMCLK FREQUENCIES........................................................232

1.

Using ASTCR .................................................................................................................................232

2.

ASTCR I/O Cycle Type and Hold Times .........................................................................................233

3.

Example.......................................................................................................................................... 233

D. EXPANDING PC-STYLE I/O TO 32 BITS ..........................................................................234

1.

32-Bit I/O ........................................................................................................................................234

E. CL-PS7500FE VIDEO CLOCK SOURCES.........................................................................236

1.

Introduction ..................................................................................................................................... 236

2.

Clock Sources ................................................................................................................................236

3.

Using the Phase Comparator .........................................................................................................237

4.

Phase Comparator Reset ...............................................................................................................240

4.1

Reset Procedure.............................................................................................................240

F. CL-PS7500FE TEST MODES..............................................................................................241

1.

Introduction ..................................................................................................................................... 241

2.

Test Modes Description ..................................................................................................................241

G. CL-PS7500FE PINOUT DIFFERENCES FROM THE ARM7500 ......................................243

1.

Introduction ..................................................................................................................................... 243

INDEX .................................................................................................................................245

June 1997

ADVANCE DATA BOOK v2.0

11

TABLE OF CONTENTS

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