CL-PS7500FE-QC-A Просмотр технического описания (PDF) - Cirrus Logic

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CL-PS7500FE-QC-A

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

1.2 Block Diagram

MAIN

CLOCKS/CONTROL

RESET

VIDEO

CLOCKS AND

CONTROL

SOUND

SYSTEM

REFERENCE

CURRENT

VIDEO

OUTPUTS

POWER

MANAGEMENT

EXTERNAL

INTERRUPT

SOURCES

A-TO-D

CONVERTORS

KBD/MOUSE

INTERFACE

SNA

CPUCLK

MEMCLK

I_OCLK

nPOR

nRESET

RESET

HCLK

VCLKI

VCLKO

PCOMP

SCLK

WS

SDO

SDCLK

VIREF

HSYNC

VSYNC

ECLK

ED[7:0]

RGB OUTPUTS

nTEST

OD[1:0]

SYNC

ID

nEVENT1

nEVENT2

OSCDELAY

OSCPOWER

nINT6

nINT3

nINT8

INT7

INT9

nINT4

INT5

nINT1

INT2

ATODREF

ATOD[3:0]

MSECLK

MSEDAT

KBCLK

KBDAT

CL-PS7500FE

LA[28:0]

LNBW

D[31:0]

nROMCS

nWE

RA[11:0]

nCAS[3:0]

nRAS[3:0]

CLK2

CLK8

REF8M

CLK16

IOP[7:0]

BD[15:0]

SETCS

nCCS

nCDACK

TC

nPCCS2

nPCCS1

nSIOCS1

nMSCS

nEASCS

nSIOCS2

nBLO

nWBE

nRBE

nBLI

nIORQ

nIOGT

nIOR

nIOW

IORNW

nXIPLATCH

nXIPMUX16

READY

LATCHED

ADDRESS

BUS AND

DATA

BUS

I/O CHIP

SELECTS

I/O R/W

CONTROL

14

PIN INFORMATION

ADVANCE DATA BOOK v2.0

June 1997

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