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L9805 Просмотр технического описания (PDF) - STMicroelectronics

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L9805 Datasheet PDF : 103 Pages
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L9805
3.4 MISCELLANEOUS REGISTER
(MISCR)
The Miscellaneous register allows the user to se-
lect the Slow operating mode and to set the clock
division prescaler factor. Bits 3, 4 determine the
signal conditions which will trigger an interrupt re-
quest on I/O pins having interrupt capability.
Register Address: 0020h — Read /Write
Reset Value:0000 0000 (00h)
b7 b6 b5 b4 b3 b2 b1 b0
b0 - Slow Mode Select
0- Normal mode - Oscillator frequency / 2
(Reset state)
1- Slow mode (Bits b1 and b2 define the prescaler
factor)
b1, b2 - CPU clock prescaler for Slow Mode
b2 b1 Option
0 0 Oscillator frequency / 4
1 0 Oscillator frequency / 8
0 1 Oscillator frequency / 16
1 1 Oscillator frequency / 32
b4 b3 Option
0 0 Falling edge and low level (Reset state)
1 0 Falling edge only
0 1 Rising edge only
1 1 Rising and Falling edge
The selection issued from b3/b4 combination is
applied to PA[0]..PA[7],PB0,PB1 external inter-
rupt. The selection can be made only if I bit in CC
register is reset (interrupt enabled).
b3, b4 can be written only when the Interrupt Mask
(I) of the CC (Condition Code) register is set to 1.
b5,b6,b7 = not used
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