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L9805

Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Full H-Bridge Driver

STMicroelectronics 

L9805

3.3 WATCHDOG SYSTEM (WDG)

3.3.1 Introduction

The Watchdog is used to detect the occurrence of

a software fault, usually generated by external in-

terference or by unforeseen logical conditions,

which causes the application program to give up its

normal sequence. The Watchdog circuit generates

an MCU reset on expiry of a programmed time pe-

riod, unless the program refreshes the counter’s

contents before it is decremented to zero.

3.3.2 Main Features

– Programmable Timer (64 increments of 12,288

CPU clock)

– Programmable Reset

– reset (if watchdog activated) after an HALT in-

struction or when bit timer MSB reaches zero

– Watchdog Reset indicated by status flag.

3.3.3 Functional Description

The counter value stored in the CR register (bits

T6:T0), is decremented every 12,288 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

Figure 8. Functional Description

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 1):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T5:T0 bit contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 3. Watchdog Timing (fOSC = 16 MHz)

WDG Register initial

value

7Fh

C0h

WDG timeout period (ms)

98.3

1.54

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction

will generate a Reset.

RESET

WATCHDOG STATUS REGISTER (WDGSR)

WDGF

WATCHDOG CONTROL REGISTER (WDGCR)

WDGA MSB

LSB

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

÷12288

17/103

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