L9805 Просмотр технического описания (PDF) - STMicroelectronics
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L9805 Datasheet PDF : 103 Pages
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L9805
WATCHDOG SYSTEM (Cont’d)
The Watchdog delay time is defined by bits 5-0 of
the Watchdog register; bit 6 must always be set in
order to avoid generating an immediate reset.
Conversely, this can be used to generate a soft-
ware reset (bit 7 = 1, bit 6 = 0).
The Watchdog must be reloaded before bit 6 is dec-
remented to “0” to avoid a Reset. Following a Re-
set, the Watchdog register will contain 7Fh (bits 0-
7).
If the circuit is not used as a Watchdog (i.e. bit 7 is
never set), bits 6 to 0 may be used as a simple 7-
bit timer, for instance as a real time clock. Since no
reset will be generated under these conditions, the
Watchdog control register must be monitored by
software.
A flag in the watchdog status register indicates if
the last reset is a watchdog reset or not, before
clearing by a write of this register.
3.3.4 Register Description
3.3.4.1 Watchdog Control Register
(WDGCR)
Register Address: 002Ah — Read /Write
Reset Value: 0111 1111 (7Fh)
7
0
WDGA T6 T5 T4 T3 T2 T1 T0
b7 = WDGA: Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled.
b6-0 =T6-T0: 7 bit timer (Msb to Lsb)
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
become cleared).
3.3.4.2 Watchdog Status Register
(WDGSR)
Register Address: 002Bh — Read/Write
Reset Value(*): 0000 0000 (00h)
7
0
-
-
-
-
-
-
-
WDGF
b7-1 = not used
b0 = WDGF: Watchdog flag. Set by a Watchdog
Reset, cleared by software (writing zero) or Power
On / Low Voltage Reset. This flag is useful for dis-
tinguishing Power On / Low Voltage Reset and
Watchdog Reset.
(*): Except in the case of Watchdog Reset.
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