CS5460 Просмотр технического описания (PDF) - Cirrus Logic

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CS5460

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5460

3.4 System Initialization

A software or hardware reset can be initiated at any

time. The software reset is initiated by writing a

logic 1 to the RS (Reset System) bit in the configu-

ration register, which automatically returns to logic

0 after reset. At the end of the 32nd SCLK (i.e., 8 bit

command word and 24 bit data word) internal syn-

chronization delays the loading of the configura-

tion register by 3 or 4 DCLK (MCLK/K). Then the

reset circuit initiates the reset routine on the 1st fall-

ing edge of MCLK. A hardware reset is initiated

when the RESET pin is forced low with a minimum

pulse width of 50 ns. The RESET signal is asyn-

chronous requiring no MCLKs for the part to detect

and store a reset event. Once the RESET pin is in-

active the internal reset circuitry remains active for

5 MCLK cycles to insure resetting the synchronous

circuitry in the device. The modulators are held in

reset for 12 MCLK cycles after RESET becomes

inactive. The internal registers (some of which drive

output pins) will be reset to their default values on

the first MCLK received after detecting a reset event

(see Table 2). After a reset, the on-chip registers are

initialized to the following states and the converter

is placed in the command mode where it waits for a

valid command.

Configuration Register:

Offset Register:

Gain Registers

Pulse-Rate Register:

Cycle-Counter Register:

Timebase Register:

Status Register:

Mask Register

Signed Registers

Unsigned Registers

0x000001

0x000000

0x400000

0x0FA000

0x000FA0

0x800000

0x000001

0x000000

0x000000

0x000000

Table 2. Internal Registers Default Value

20

DS279PP5

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