CDP1854 Просмотр технического описания (PDF) - Intersil

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CDP1854

Programmable Universal Asynchronous Receiver/Transmitter (UART)

Intersil 

CDP1854A, CDP1854AC

Block Diagram

Mode Input High (Mode = 1)

TRANSMITTER SECTION

CDP1802

INTERFACE

RECEIVER SECTION

SDO

25

PARITY

GEN

40 24 39

TRANSMITTER

TIMING &

CONTROL

34 18 16

38 37 17

RECEIVER

TIMING &

CONTROL

1, 2 = VDD

3 = VSS

21 = CLEAR

36 = NC

SHIFT

20

REGISTER SDI

RECEIVER

HOLDING

REGISTER

TRANSMITTER

SHIFT

REGISTER

TRANSMITTER

HOLDING

REGISTER

CONTROL

REG

TRANSMITTER BUS

(26 - 33)

(SEE NOTE 1)

SELECT

LOGIC

23 4 35

INT

13

STATUS

REGISTER

22 14 15 19

(SEE NOTE 1)

MUX

THREE-STATE

DRIVERS

RECEIVER BUS

(5-12)

(SEE NOTE 1)

NOTE: 1. User Interconnect

FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)

5-44

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