CDP1854 Просмотр технического описания (PDF) - Intersil
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CDP1854 Datasheet PDF : 21 Pages
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CDP1854A, CDP1854AC
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF,
(See Figure 3)
LIMITS
CDP1854A
CDP1854AC
PARAMETER
VDD
(NOTE 1) (NOTE 2) (NOTE 1) (NOTE 2)
(V)
TYP
MAX
TYP
MAX
TRANSMITTER TIMING - MODE 1
Minimum Clock Period
tCC
5
10
250
310
250
310
125
155
-
-
Minimum Pulse Width
Clock Low Level
tCL
5
10
100
125
100
125
75
100
-
-
Clock High Level
tCH
5
10
100
125
100
125
75
100
-
-
TPB
tTT
5
100
150
100
150
10
50
75
-
-
Minimum Setup Time
TPB to Clock
tTC
5
10
175
225
175
225
90
150
-
-
Propagation Delay Time
Clock to Data Start Bit
tCD
5
10
300
450
300
450
150
225
-
-
TPB to THRE
tTTH
5
10
200
300
200
300
100
150
-
-
Clock to THRE
tCTH
5
10
200
300
200
300
100
150
-
-
NOTES:
1. Typical values for TA = 25oC and nominal voltages.
2. Maximum limits of minimum characteristics are the values above which all devices function.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
T CLOCK
WRITE (TPB)
(NOTE 3)
THRE
tTC
tTT
tTTH
SDO
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
tCC
tCH
tCL
1 2 3 4 5 6 7 14 15 16 1 2 3 4
tCD
tCTH
tCD
1ST DATA BIT
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The Transmitter Shift Register is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTC after
the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later.
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0.
FIGURE 3. TRANSMITTER TIMING DIAGRAM - MODE 1
5-51
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